1. Field of the Invention
The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a recessed channel array transistor (RCAT) with neck fins and a method of manufacturing the same.
2. Description of the Prior Art
As semiconductor memory devices become more highly integrated, memory cells gradually become smaller. As such, a variety of efforts have been made to form a memory device having a desired cell capacitance and/or to increase a cell transistor characteristic in smaller memory cells. As the size of the memory cell decreases, a cell transistor having a smaller size may be needed. To implement a cell transistor having desired characteristics in spite of the miniaturization of the memory cell, a method of controlling the concentration of impurities in a diffusion layer has been proposed. As the length of a channel decreases, controlling the depth of the diffusion layer of a transistor becomes increasingly difficult in a variety of thermal treatment processes during a device manufacturing process. As an effective channel length and/or a threshold voltage decrease, a short channel effect occurs. The short channel effect causes problems in the operation of the cell transistor.
To address the above problem, a recessed channel array transistor (RCAT), in which a recess is formed on a surface of a substrate and a gate of a transistor is formed in the recess, is developed. Because the gate is disposed in the recess formed in the substrate, the distance between a source and a drain is extended such that the effective channel length increases, thereby improving the short channel effect.
However, as NAND flash memory is further scaled, parasitic capacitance coupling between the selected wordline and adjacent floating gates (FG) and control gates (CG) in RCAT becomes problematic. Because of the parasitic coupling, the adjacent cells are more prone to Vpass disturb than the other cells that also share the common bitline with the cells being programmed. This phenomenon is also referred to as Edge Wordline Disturb (EWD), represented a reliability issue on traditional Flash NAND memories evidenced as an unwanted positive threshold voltage shift of all the cells belonging to the first wordline (WL0) connected to the Ground Select Transistor (GSL).
One conventional approach to solve wordline Disturb is implantation control for forming asymmetric junction (deeper Dgt junction), but this approach would reduce the window of cell side junction control. The other approach is directed to the deeper fin structure, but the process of forming deeper fin is apt to damage the array bottom and change the performance.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to minimize the adjacent wordline disturb over the range of Vpgm voltages.